Leopard
KP Labs
Leopard is a flight-proven Data Processing Unit supporting the full payload data handling chain on-board, designed for Edge AI in micro and mini satellites.
Typed specifications70 values
Discloses 11 of 13 fields engineers filter by in this category (category median 5).
- Processor
- AMD Zynq UltraScale+ MPSoC ZU6EG | ZU9EG | ZU15EG Quad ARM Cortex-A53 CPU datasheet p.2 Dual ARM Cortex-R5
- Mass
- 725 g datasheet p.2
- CPU clock
- 1 200 MHz datasheet p.2 1 200 MHz ARM Cortex-A53
- Envelope (L×W×H)
- 95.89 x 90.17 x 47.2 mm datasheet p.2
- RAM
- 16 384 MB datasheet p.2 16 384 MB PS-DDR4 (with ECC) | Boot flash (NOR)
- Mass storage
- 4 GB datasheet p.2 320 GB 2 x pSLC flash-based mass data storage (redundant) | 4 GB SLC NAND flash memory (with EDAC)
- Operating system
- 64-bit Linux (Yocto based) datasheet p.2 Linux 64-bit Linux (Yocto based)
- Supply voltage
- 7 V min · datasheet p.2 14 V max | 7–14 V | 7–14 V Supply voltage 7 to 14 V
- Power consumption
- 20 W max · datasheet p.2 5 W min | 5 W min · depending on workload | 20 W max · depending on workload
- Data interface
- CAN datasheet p.2 other 2 x PPS input | SpaceWire 2 x SpaceWire | Ethernet 3 x Gigabit Ethernet 1000BASE-T | other CameraLink Base/LVDS +19
- Operating temperature
- -25–75 °C datasheet p.2
- Radiation tolerance (TID)
- 20 krad datasheet p.2 20 krad min · > 20 kRad (with enclosure)
- Processor architecture
- ARM Cortex-R Dual ARM Cortex-R5 (lock-step) · datasheet p.2 ARM Cortex-A Quad ARM Cortex-A53
- Board format
- PC/104 PC/104 form-factor with efficient thermal interface · datasheet p.2
- Flight software support
- CSP over CAN (Supervisor TMTC); SDK and Reference Designs for software and FPGA development; compatible with Vitis AI Deep Learning Accelerator datasheet p.2
- Radiation and fault mitigation
- TMR in FPGA datasheet p.2 EDAC / ECC on RAM 16 GiB PS-DDR4 with ECC | ECC on flash 4 GiB SLC NAND flash with EDAC | other 64 MB Boot flash (NOR) with TMR | other Independent Supervisor: telemetry and control, FDIR, software… +1
- Flight heritage
- Flight-proven Data Processing Unit; qualified for launch and space environment at NASA GEVS levels datasheet p.1
- Satellite class
- nanosat 1-10 kg Edge Processing for Nano and Micro Satellites · datasheet p.1 microsat 10-100 kg Edge Processing for Nano and Micro Satellites
- Cores
- 4 ARM Cortex-A53 · datasheet p.2 2 ARM Cortex-R5 (lock-step)
- FPGA
- FPGA for custom function implementation (AMD Zynq UltraScale+ MPSoC) datasheet p.2
- GPIO lines
- 1 datasheet p.2
- RAM type
- DDR4 16 GiB PS-DDR4 with ECC · datasheet p.2
- Program / boot memory
- 64 MB Boot flash (NOR) with TMR · datasheet p.2
- Redundancy
- other redundant mass memory (2 x 320 GB) · datasheet p.1
- Data interface speed
- 1 000 Mbps 3 x Gigabit Ethernet 1000BASE-T · datasheet p.2
Each value is typed with its unit and measurement condition and cites the datasheet page it was taken from. Nothing is guessed: a field that is absent here has not been published by the manufacturer. machine-extracted ✓ checked by NewSpace Market ✓ manufacturer confirmed by the manufacturer.
As published by the supplier12 lines, in the manufacturer's own wording
- Processing cores
- AMD Zynq UltraScale+ MPSoC ZU6EG | ZU9EG | ZU15EG
- CPU
- Quad ARM Cortex-A53 1.2 GHz
- FPGA
- for custom function implementation
- PS-DDR4 Memory
- 16 GiB (with ECC)
- Boot flash
- 64 MB (NOR) with TMR
- NAND flash memory
- 4 GiB SLC (with EDAC)
- Mass data storage
- 2 x 240 GiB pSLC flash-based (redundant)
- Supervisor TMTC interface
- CAN with CSP, UART/RS422/485
- PL-connected interfaces
- LVDS, GPIOs and QuadGTH transceivers
- Supply voltage
- 7 to 14 V
- Power consumption
- 5 W to 20 W – depending on workload
- Form-factor
- PC/104
About
Leopard is an advanced Data Processing Unit for satellites, specifically designed for Edge AI in Nano and Micro Satellites. It features a CPU + FPGA architecture with redundant mass memory and industry-standard interfaces, all within a low SWaP (Size, Weight, and Power) solution. The unit supports both off-the-shelf and custom Interface Boards, allowing for seamless integration with various spacecraft platforms and payload components. Its architecture includes a Supervisor for telemetry and control, FDIR, and software recovery, alongside a Processing Node for data processing and memory. The processing cores are AMD Zynq UltraScale+ MPSoC (ZU6EG | ZU9EG | ZU15EG) with a Quad ARM Cortex-A53 CPU at 1.2 GHz and Dual ARM Cortex-R5 (lock-step), plus an FPGA for custom function implementation. It boasts 16 GiB PS-DDR4 (with ECC), 64 MB Boot flash (NOR) with TMR, 4 GiB SLC NAND flash memory (with EDAC), and 2 x 240 GiB pSLC flash-based mass data storage (redundant). The Leopard DPU is compatible with Vitis AI Deep Learning Accelerator and runs a 64-bit Linux (Yocto based) operating system, fully reconfigurable in-orbit. It is presented in a PC/104 form-factor with an efficient thermal interface, making it integration-ready for various applications like Earth Observation, Space Situational Awareness, and Autonomous Rendezvous & Docking.
Documentation
Need the full ICD, test reports or a specific revision? Ask the supplier directly.