RT ProASIC3
Microchip Technology / Microsemi (Space)
RT ProASIC3 FPGAs are flash-based, radiation-tolerant, reprogrammable, and nonvolatile field-programmable gate arrays designed for low-power space applications requiring up to 350 MHz operation and up to 3 million system gates.
Technical specifications
- Device
- RT3PE600L
- System gates
- 600,000
- Logic tiles
- 13,824
- Core ram blocks
- 24
- Core ram kbits (1,024 bits)
- 108
- Flashrom bits
- 1,000
- Routed
- 18
- Plls
- 6
- I/o banks
- 8
- User i/os (maximum)
- 270
- I/o registers
- 810
- Speed grades
- Std., -1
- Screening level
- B, E
- Ccga/lga
- 484
- Cqfp
- 256
- Device (2)
- RT3PE3000L
- System gates (2)
- 3,000,000
- Logic tiles (2)
- 75,264
- Core ram blocks (2)
- 112
- Core ram kbits (1,024 bits) (2)
- 504
- Flashrom bits (2)
- 1,000
- Routed (2)
- 18
- Plls (2)
- 6
- I/o banks (2)
- 8
- User i/os (maximum) (2)
- 620
- I/o registers (2)
- 1,860
- Speed grades (2)
- Std., -1
- Screening level (2)
- B, E
- Ccga/lga (2)
- 484, 896
- Cqfp (2)
- 256
- Flash cells (heavy ions) test limit
- 96 MeV-cm2/mg
- Flash cells (heavy ions) onset LET
- No errors observed
- Flash cells (heavy ions) saturation cross-section
- No errors observed
- D-type flip-flops (heavy ions) test limit
- 96 MeV-cm2/mg
- D-type flip-flops (heavy ions) onset LET
- 6 MeV-cm2/mg
- D-type flip-flops (heavy ions) saturation cross-section
- 2E-7 cm2 per flip-flop
- Sram memory (heavy ions) test limit
- 96 MeV-cm2/mg
- Sram memory (heavy ions) onset LET
- 1 MeV-cm2/mg
- Sram memory (heavy ions) saturation cross-section
- 4E-8 cm2 per memory bit
- Flashrom memory (heavy ions) test limit
- 96 MeV-cm2/mg
- Flashrom memory (heavy ions) onset LET
- No errors observed
- Flashrom memory (heavy ions) saturation cross-section
- No errors observed
- D-type flip-flops (63.5 mev protons) saturation cross-section
- 5E-14 cm2 per flip-flop
- Sram memory (63.5 mev protons) saturation cross-section
- 1E-13 cm2 per memory bit
- Global clock set test limit
- > 70 MeV-cm2/mg
- Global clock set onset LET
- 4 MeV-cm2/mg
- Global clock set saturation cross-section
- 2E-6 cm2 per global clock network
- I/o bank set test limit
- > 70 MeV-cm2/mg
- I/o bank set onset LET
- 7 MeV-cm2/mg
- I/o bank set saturation cross-section
- 2E-6 cm2 per I/O bank
About
RT ProASIC3 FPGAs are the industry’s first flash-based, radiation-tolerant FPGAs specifically developed for low-power space applications. Unlike Microsemi’s other radiation-tolerant FPGAs that use antifuse technology, RT ProASIC3 devices utilize flash cells to store configuration information. This flash-based interconnect technology offers several advantages for space-flight electronic hardware designers, including reprogrammability (allowing design changes without removing the FPGA from the board, facilitating prototyping, and enabling last-minute design updates), nonvolatility (eliminating the need for external code-storage devices, saving board space and mass, and enabling immediate power-up operation without a boot sequence), and inherent immunity to single-event upsets (SEU) in the flash cells under heavy ion radiation, thus removing the need for triple-chip redundancy for configuration upset mitigation.
These FPGAs are available in two densities: RT3PE600L (600,000 system gates) and RT3PE3000L (3,000,000 system gates), allowing integration of large or medium-sized designs. They use the same silicon design and UMC 0.13 µm process as the commercial ProASIC3EL family. RT ProASIC3 FPGAs are assembled in hermetically-sealed, ceramic packages, available as Quad Flat Pack (CQFP), Column Grid Array (CG, with Six Sigma solder columns), or Land Grid Array (LG, no solder columns). Qualification, inspection, assembly, and testing are performed in accordance with MIL-STD-883 Class B.
The devices have been extensively tested for various radiation effects, including Single Event Latch-Up (SEL) with no events observed up to a projected LET threshold of 68 MeV-cm2/mg, Single-Event Upset (SEU) in logic tiles, embedded SRAM, and PLLs (flash cells and FlashROM showed no SEU to LET rates > 96 MeV-cm2/mg), and Single-Event Transient (SET) on global clock networks and I/O banks. Mitigation strategies for SEEs, such as triple-module redundancy (TMR) for clock networks, I/O banks, and D-type flip-flops, are discussed. Total Ionizing Dose (TID) testing in gamma ray environments showed a 10% increase in propagation delay at 25 to 30 kRad. Each wafer lot undergoes sample testing for TID effects in compliance with MIL-STD-883 Class B test method 1019.
Documentation
No public datasheet yet — request the datasheet / ICD from the supplier.