HARDWARE / PRODUCTUpdated 25 Jul 2026

RTSX-SU

Microchip Technology / Microsemi (Space)
RTSX-SU

RTSX-SU is a family of high-reliability, radiation-tolerant antifuse-based FPGAs derived from Microsemi's commercial SX-A family, built for space applications.

Key figurescomparable across the catalogue

Power
0.068 W

Normalised to common units so this product can be compared with others in its category. The supplier's own wording is below.

As published by the supplier

System performance
230 MHz (310 MHz internal)
Standby power consumption
Up to 68 mW
Operating voltage
3.3 V and 5.0 V mixed voltage
Configurable i/o support
3.3 V/5 V PCI, LVTTL, TTL, and CMOS
Input tolerance / drive strength
5 V input tolerance and 5 V drive strength
Security
Secure programming technology prevents reverse engineering and design theft
Resource utilization
100% circuit resource utilization with 100% pin locking
In-system diagnostics
Unique in-system diagnostic and verification capability with Silicon Explorer II
Prototyping
Low-cost prototyping option, deterministic, user-controllable timing
Boundary scan
JTAG boundary scan testing in compliance with IEEE Standard 1149.1, dedicated JTAG Reset (TRST) pin
Programming technology
Highly reliable, nonvolatile antifuse technology
Gate count
32,000 to 72,000 ASIC gates (48,000 to 108,000 system gates)
User-programmable i/os
Up to 360
Packages
Hermetically-sealed packages for space applications (CQFP, CCGA/LGA, CCLG)
SEU hardening
SEU-Hardened registers eliminate the need to implement TMR
SEU immunity
Immune to Single-Event Upsets (SEU) to LETTH > 40 MeV-cm2/mg
SEU rate
< 1E-10 upset/bit-day in worst-case geosynchronous orbit
Total ionizing dose (TID)
Up to 100 krad (Si) - parametric performance supported with lot-specific test data
Single-event latch-up (SEL)
Immunity
Device: rtsx32su - typical gates
32,000
Device: rtsx72su - typical gates
72,000
Device: rtsx32su - system gates
48,000
Device: rtsx72su - system gates
108,000
Device: rtsx32su - logic modules
2,880
Device: rtsx72su - logic modules
6,036
Device: rtsx32su - combinatorial cells
1,800
Device: rtsx72su - combinatorial cells
4,024
Device: rtsx32su - SEU-hardened register cells (Dedicated Flip-Flops)
1,080
Device: rtsx72su - SEU-hardened register cells (Dedicated Flip-Flops)
2,012
Device: rtsx32su - maximum flip-flops
1,980
Device: rtsx72su - maximum flip-flops
4,024
Device: rtsx32su - maximum user i/os
227
Device: rtsx72su - maximum user i/os
360
Device: rtsx32su - clocks
3
Device: rtsx72su - clocks
3
Device: rtsx32su - quadrant clocks
0
Device: rtsx72su - quadrant clocks
4
Device: rtsx32su - speed grades
Std., -1
Device: rtsx72su - speed grades
Std., -1
Device: rtsx32su - temperature grades
B, E, M
Device: rtsx72su - temperature grades
B, E
Device: rtsx32su - cqfp package (pin count)
84, 208, 256
Device: rtsx72su - cqfp package (pin count)
208, 256
Device: rtsx32su - ccga package (pin count)
624
Device: rtsx32su - cclg package (pin count)
256

About

RTSX-SU RadTolerant FPGAs are enhanced versions of Microsemi’s commercial SX-A family of devices, specifically designed for improved radiation performance. They feature SEU-hardened D-type flip-flops that provide the benefits of Triple Module Redundancy (TMR) without the associated overhead, making them a unique offering for space applications. The devices are manufactured using 0.25 µm technology at the United Microelectronics Corporation (UMC) facility in Taiwan and offer radiation survivability far in excess of typical CMOS devices. The RTSX-SU architecture is derived from the SX-A sea-of-modules architecture, enhanced with SEU-hardened flip-flops, wider clock lines, and stronger clock drivers to improve upset and total-dose performance in radiation environments. The entire chip floor is covered with a grid of logic modules, with virtually no chip area lost to interconnect or routing, giving 100% circuit resource utilization and 100% pin locking. Key features include 230 MHz system performance (310 MHz internal), very low standby power consumption (up to 68 mW), 3.3 V and 5.0 V mixed-voltage operation, configurable I/O supporting 3.3V/5V PCI, LVTTL, TTL, and CMOS, 5 V input tolerance and drive strength, secure programming technology to prevent reverse engineering and design theft, in-system diagnostic and verification capability with Silicon Explorer II, low-cost prototyping with deterministic user-controllable timing, JTAG boundary scan testing per IEEE 1149.1 with a dedicated JTAG Reset (TRST) pin, and highly reliable nonvolatile antifuse technology. Devices offer 32,000 to 72,000 ASIC gates (48,000 to 108,000 system gates) and up to 360 user-programmable I/Os, available in hermetically-sealed packages (CQFP, CCGA/LGA, CCLG) for space applications. Radiation performance includes SEU-hardened registers that eliminate the need for TMR, immunity to Single-Event Upsets to LETth > 40 MeV-cm2/mg, an SEU rate of less than 1E-10 upset/bit-day in worst-case geosynchronous orbit, up to 100 krad (Si) Total Ionizing Dose with lot-specific test data support, and Single-Event Latch-Up (SEL) immunity. The family comprises two devices, RTSX32SU and RTSX72SU, differing in gate count, logic resources, and I/O count.

Documentation

No public datasheet yet — request the datasheet / ICD from the supplier.

Source: web.archive.org ↗

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