LEON5 SPARC V8 Processor IP Core
Gaisler
Configurable synthesizable VHDL SPARC V8 processor IP core for FPGA and deep-submicron ASIC SoC designs.
Technical specifications
- Architecture
- SPARC V8, 32-bit
- Delivery
- Synthesizable VHDL IP core (GRLIB)
- Target technologies
- High-end FPGA, deep-submicron ASIC
- Compatibility
- Backward compatible with LEON3/LEON4 software
- Status
- Available
- Frequency
- 250 MHz
- Interface
- PCI100 SDRAM
- Interface (2)
- SpaceWire router with SpaceWire links: 300 Mbit/s
- Frequency (2)
- 33 MHz PCI 2.3
- Interface (3)
- Ethernet: 10/100/1000 Mbit MACs
About
The LEON5 is a synthesizable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture, part of the GRLIB IP Library. The model is highly configurable and suitable for system-on-chip (SoC) designs, primarily targeting high-end FPGAs and deep-submicron ASIC technologies. LEON5 provides backward compatibility for most software implementations that have targeted LEON3 and LEON4 processors and sets a new standard in the LEON family for processing performance and fault tolerance, suited for advanced payloads and platform units in extreme environments. The processor model continues to be extended, with planned extensions including a more advanced version featuring virtualization and higher-performance bus interconnect. For legacy or less performant technologies, LEON3 remains the recommended choice.
Documentation
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