NOEL-V RISC-V Processor IP Core
Gaisler
Configurable synthesizable RISC-V processor IP core for space, offering dual-issue execution and flight-proven design.
Technical specifications
- Architecture
- RISC-V
- Issue width
- Up to dual-issue (2 instructions/cycle)
- Delivery
- Synthesizable VHDL IP core (GRLIB)
- Heritage
- Flight-proven in Earth orbit
- Status
- Available
About
The NOEL-V is a synthesizable VHDL model of a processor implementing the RISC-V architecture, part of the GRLIB IP Library. It can be implemented as a dual-issue processor, executing up to two instructions per cycle in parallel. NOEL-V is designed for space applications with a high-performance, fault-tolerant design. Built on the RISC-V architecture, it offers flexibility and customization for SoC designers to tailor solutions to specific needs, while giving software developers access to the broad RISC-V software and tooling ecosystem. NOEL-V has been adopted in several ASIC products and is flight-proven, having demonstrated its capabilities in Earth orbit.
Documentation
No public datasheet yet — request the datasheet / ICD from the supplier.
