SCFE6120 6U OpenVPX FPGA Carrier Board
Mercury Systems
The EnsembleSeries™ SCFE6120 is a versatile OpenVPX™ FPGA processing module designed for high performance and agile system integration, incorporating Virtex® Ultrascale+™ FPGA processing power.
Typed specifications41 values
Discloses 6 of 13 fields engineers filter by in this category (category median 5).
- Processor
- Two Xilinx Virtex® Ultrascale+™ VU9P Prosecutors datasheet p.2 One Xilinx Zynq® Ultrascale+™ ZU11EG Governor
- Envelope (L×W×H)
- Single Slot 6U OpenVPX form factor product page
- RAM
- 20 480 MB datasheet p.2 20 480 MB 20 GB of DDR4 SDRAM
- Mass storage
- 2 GB datasheet p.3 2 GB eMMC, Zynq PS memory | 2 GB Flash, Zynq PL memory | 2 GB
- Operating system
- embedded Linux datasheet p.3 Linux Zynq subsystem loaded with embedded Linux, Linux BSP supplied
- Data interface
- PCIe datasheet p.2 LVDS 105 LVDS pairs per FMC site, LVDS pairs x16 on P5, P1/P2 LVDS… | PCIe AXI4-Stream data plane routed to external interfaces such as … | Ethernet Ethernet switch: 1000BASE-T x3 (incl. RJ45 front panel), 1000… | GPIO GPIO_SE x4 single-ended and GPIO_DP x8 differential pair gene… +11
- Operating temperature
- -40–71 °C conduction-cooled, Rugged L3, at module edge · datasheet p.3
- Board format
- 6U VPX Single slot 6U OpenVPX form factor, ANSI/VITA 65-2010 (R2013) · datasheet p.1
- Connector
- Two FMC+ connectors (ANSI/VITA 57.4 sites, single and double width FMC cards); RJ45 front panel; VITA 67 on P6 datasheet p.1
- Survival temperature
- -55–125 °C storage · datasheet p.3
- Shock qualification
- 80 g x and y axes, 11 ms 1/2-sine pulse, 3 positive, 3 negative · datasheet p.3 80 g x and y-axes | 50 g z-axis, 11 ms 1/2-sine pulse, 3 positive, 3 negative
- FPGA
- Two Xilinx Virtex Ultrascale+ VU9P "Prosecutors" datasheet p.1 One Xilinx Zynq Ultrascale+ ZU11EG "Governor"
- RAM type
- DDR4 DDR4 SDRAM, banks operate at 1200MHz DDR · datasheet p.1 FRAM FRAM 4Mbit per Prosecutor memory bank and in Zynq PL memory
- Program / boot memory
- 0.5 MB FRAM 4Mbit · datasheet p.2
- Data interface speed
- 16 300 Mbps max · GTH multi-gigabit transceiver, per lane · datasheet p.2 32 750 Mbps max · GTY multi-gigabit transceiver, per lane
Each value is typed with its unit and measurement condition and cites the datasheet page it was taken from. Nothing is guessed: a field that is absent here has not been published by the manufacturer. machine-extracted ✓ checked by NewSpace Market ✓ manufacturer confirmed by the manufacturer.
As published by the supplier15 lines, in the manufacturer's own wording
- Dimensions
- Single Slot 6U OpenVPX form factor
- FMC sites
- Two FMC ANSI/VITA 57.4 sites
- FPGA processors
- Two Xilinx Virtex® Ultrascale+™ VU9P Prosecutors
- FPGA processors (2)
- One Xilinx Zynq® Ultrascale+™ ZU11EG Governor
- Memory
- 20 GB of DDR4 SDRAM
- Max Rate of Change
- 10ºC/min
- Operating humidity
- 5-95%, non-condensing
- Storage humidity
- 100% condensing
- Operating altitude
- 0-70,000ft
- Storage altitude
- 0-70,000ft
- Vibration (Random)
- 0.1 g2/Hz; 5-2000 Hz, 1 hr/axis
- Vibration (Sine)
- 10G peak; 5-2000 Hz, 1 hr/axis
- Shock
- z-axis: 50g; x and y-axes: 80g
- Salt/Fog
- 10% NaCl
- DDR4 SDRAM Memory Banks operation
- 1200 MHz DDR
About
The EnsembleSeries™ SCFE6120 is a versatile OpenVPX™ FPGA processing module designed for high performance and agile system integration. Incorporating Virtex® Ultrascale+™ FPGA processing power and an updated architecture, this advanced module maximizes performance by locating the processing subsystem directly in the data path. Two FMC ANSI/VITA 57.4 sites enable maximum customization and can support high-speed digitization cards. It features a multi-channel, highly configurable FMX carrier, processing subsystems in the data path for maximum performance, OpenVPX™ compliance for easy integration, and multiple high-reliability cooling options. This configurable, low-latency processing module is ideal for high performance and agile system integration.
Documentation
Need the full ICD, test reports or a specific revision? Ask the supplier directly.