Payload Data Handling System VPDHS
VECTRONIC Aerospace GmbH
The VPDHS is a Payload Data Handling System developed by VECTRONIC Aerospace for small satellite applications, designed to receive, store, compress, and format payload data for transmission to ground stations.
Key figurescomparable across the catalogue
- Mass
- 2.3 kg
- Power
- 15 W
- Largest dimension
- 290 mm
Normalised to common units so this product can be compared with others in its category. The supplier's own wording is below.
As published by the supplier
- Dimensions
- 290 mm x 192 mm x 34 mm
- Mass
- 2.3 kg
- Mounting pattern
- 6 x M4
- Power consumption
- Max 15 W
- Power supply
- 9 V – 18 V, 18 V – 36 V
- Signal interface
- RS422 / RS485
- Signal characteristics
- Serial asynchronous
- Connector type
- MDM-25
- Operating temp.range
- -20°C to + 70°C
- Storage temp. range
- -40°C to + 80°C
- Vibration
- 13.4 g rms
- Radiation tolerance
- > 20 krad
- Storage capacity sdram
- 4 GBytes
- Storage capacity flash
- 16 GBytes non-volatile
- Data interface
- 30 LVDS I/O @ 480 Mbps 24 SerDes inputs @ up to 2 Gbps 1 LVDS output @ 105 Mbps
- Other inputs
- Pulse-per-second synchronization
About
The VECTRONIC Aerospace Payload Data Handling System (VPDHS) is engineered for small satellite applications, focusing on efficient management of payload data, particularly from cameras. Its primary functions include receiving high-speed payload data, storing it, compressing it, and formatting it for transmission via a High Speed Interface to a ground station. The system is built on an FPGA/Microcontroller-Architecture, offering 4 GBytes of SDRAM and 16 GBytes of non-volatile Flash memory for data storage. The microcontroller serves as the System Monitor, managing the proper operation of the FPGA, monitoring internal temperatures and current consumption, and ensuring the integrity of the in-circuit programmable Flash memory content. Key tasks of the VPDHS include reception of high-speed data from two cameras via LVDS interfaces (e.g., Camera Link), optional storage in non-volatile flash memory, and an RS422 interface to the On-Board Attitude Control computer for ACS data. It also provides multiple LVDS interfaces to other on-board devices, an RS422 interface to a GPS Receiver for pulse-per-second synchronization, real-time adjustable lossy and lossless compression of imager data, CCSDS formatting for transmitted data, and a High Speed Interface to the On-Board transmitter. The FPGA bit configuration is protected against Single Event Upsets (SEU) by a SEU-Controller, managed by the System Monitor.
Documentation
Need the full ICD, test reports or a specific revision? Ask the supplier directly.