OBC PolarFire VPX
CAVU Aerospace
OBC based on PolarFire FPGA SoC in 3U VPX
Technical specifications
- Processor
- Microchip MPFS460T-1FCG1152I / MPFS460TS-1FCG1152I (with security)
- Risc-v cores
- Quad 64-bit U54 application cores + 1× E51 monitor core — >4,000 DMIPS total
- FPGA fabric
- 461k logic elements, 784 DSP blocks — flash-based, no SRAM bitstream
- Vectorblox™
- Up to 279 GOPs INT8 (V1000 config, no TMR) / 156 GOPs with synthesised TMR
- Serdes
- 20 lanes at up to 12.7 Gbps each
- Pcie
- Gen2 ×4 hard block (expansion plane)
- SEU / TID
- ZeroFIT SEU-immune; >30 krad (Si) TID; latch-up immune; SECDED BRAM ECC
- Operating temperature
- −40°C to +85°C conduction-cooled (VITA 48.2)
- Memory
- 16 GB ECC DDR4 + 4 GB LPDDR4 — 20 GB total usable memory
- Storage
- 512 GB eMMC (2× 256 GB)
- Form factor
- 3U SpaceVPX (VITA 78)
- Dimensions
- 100 × 160 mm (220 mm depth option)
- Power consumption
- 3–5 W Nominal / 7 W peak
- Supply voltage
- 5 V from backplane (P0/J0)
- Mass
- ~120 g (PCB); 500–650 g with enclosure & wedge-lock rails
- Interfaces
- GigE (RJ45), SpaceWire (Micro-D 9), I/O / Debug (Micro-D 25)
About
The PF-VPX OBC is a 3U SpaceVPX (VITA 78) System Controller designed for high-reliability space applications, built on the Microchip PolarFire® SoC (MPFS460T / MPFS460TS). It integrates a multi-core RISC-V processor with a low-power, flash-based FPGA fabric, enabling deterministic processing and flexible system design. The non-volatile FPGA architecture delivers inherent ZeroFIT single-event upset immunity, removing the need for configuration scrubbing or complex EDAC schemes required by SRAM-based devices.
Documentation
Need the full ICD, test reports or a specific revision? Ask the supplier directly.