Q8RFG3 Gen 3 RFSoC Processor
Xiphos Technologies
Third-generation space-grade RFSoC processor with 8-channel 14-bit ADC/DAC up to 6 GHz RF input and multi-device synchronization for phased-array applications.
Key figurescomparable across the catalogue
- Mass
- 0.2 kg
- Power
- 25 W
- Largest dimension
- 100 mm
Normalised to common units so this product can be compared with others in its category. The supplier's own wording is below.
As published by the supplier
- MPSoC
- Xilinx Zynq UltraScale+ ZU48DR
- Application CPU
- Quad-core ARM Cortex-A53 @ up to 1.2 GHz
- Real-Time CPU
- Dual-core ARM Cortex-R5 @ 500 MHz
- PS RAM
- 4 GB LPDDR4 DRAM (EDAC)
- PL RAM
- 4 GB DDR4 DRAM
- Storage
- 2x 128 GB eMMC
- ADC Channels
- 8
- ADC Sample Rate (max)
- 5.0 GSPS
- ADC Resolution
- 14 bit
- DAC Channels
- 8
- DAC Sample Rate (max)
- 9.85 GSPS
- DAC Resolution
- 14 bit
- RF Input Frequency (max)
- 6 GHz
- Multi-device Synchronization
- Supported (phased-array/digital beamforming)
- Dimensions
- 100 x 100 x 20 mm
- Mass
- 200 g
- Power (Typical)
- 25 to 35 W
- Input Voltage
- 5 to 15 V
- Operating Temperature
- -40 to +60 deg C
About
The Xiphos Q8RFG3 is the third-generation RFSoC processor in the Q8RF family, built on the Xilinx Zynq UltraScale+ ZU48DR. It advances the Gen 1 platform with enhanced digitization performance — 14-bit ADC resolution at up to 5.0 GSPS and 14-bit DAC resolution at up to 9.85 GSPS — as well as an extended RF input frequency range to 6 GHz and expanded decimation and interpolation options.
Multi-device synchronization support enables phased-array and digital beamforming architectures requiring coherent operation across multiple Q8RFG3 boards. The architecture enables direct RF sampling and real-time DSP without external data converters or analog front-ends. Storage is upgraded to 2×128 GB eMMC for substantially higher onboard data capacity.
Physical dimensions and mass are identical to the Q8RF (100x100x20 mm, 200g), enabling drop-in mechanical upgrades for applications where the Gen 1 Q8RF’s 4 GHz frequency ceiling or 12-bit ADC dynamic range is insufficient.
Documentation
Need the full ICD, test reports or a specific revision? Ask the supplier directly.