Q8RFG3 Gen 3 RFSoC Processor
Xiphos Technologies
Third-generation space-grade RFSoC processor with 8-channel 14-bit ADC/DAC up to 6 GHz RF input and multi-device synchronization for phased-array applications.
Typed specifications43 values
Discloses 6 of 13 fields engineers filter by in this category (category median 5).
- Mass
- 200 g datasheet p.3
- Frequency range
- 6 000 MHz RF Input Frequency, max · datasheet p.3 6 000 MHz max · RF Input | 6 000 MHz max · RF input frequency, max
- Envelope (L×W×H)
- 100 mm x 100 mm x 20 mm datasheet p.2
- Supply voltage
- 5 V min · datasheet p.3 15 V max | 5–15 V
- Power consumption
- 25 W typ., lower end of 25-35 W @ 5-15 V · datasheet p.3 35 W typ., upper end of 25-35 W @ 5-15 V | 25 W min · typ. | 35 W max · typ. | 25–35 W typ.
- Data interface
- LVDS datasheet p.3 Ethernet 100G Ethernet via GTY transceivers | LVDS 46x LVDS | SATA GTR transceivers | PCIe PCIe Gen 3 (GTY), PCIe Gen 2 (GTR) +5
- Operating temperature
- -40–60 °C Derated · datasheet p.3
- Radiation tolerance (TID)
- 30 krad datasheet p.3 30 krad flight models, TID lifetime
- Function
- SDR platform (user waveforms) SDR/Processor card · datasheet p.1
- TX chains
- 8 8x Transmit RF (8 DACs) · datasheet p.3
- RX chains
- 8 8x Receive RF (8 ADCs) · datasheet p.3
- Board format
- 100 datasheet p.3
- Waveform development
- C/C++ API Application Development Kit with standard Linux libraries for… · datasheet p.2 user FPGA bitstream logic development with standard Xilinx tools
- Connector
- Bottom RF Mezzanine Connector; Bottom I/O Mezzanine Connector datasheet p.3
- Missions flown
- 340 datasheet p.8
- TX/RX chains (as printed)
- 8x Transmit + 8x Receive RF datasheet p.3
- FPGA / SoC
- Zynq UltraScale+ RFSoC ZU48DR datasheet p.3
- Processor
- Quad-core ARM Cortex A53 Application Processing Unit at up to 1.2 GHz; Dual-core ARM Cortex-R5 @ 500 MHz datasheet p.3
- ADC / DAC resolution
- 14 bit ADC · datasheet p.3 14 bit DAC
- Sample rate
- 5 000 MSPS max · ADC · datasheet p.3 9 850 MSPS max · DAC
- Data interface speed
- 28 210 Mbps 16x GTY transceivers · datasheet p.3
- RF transceiver chip
- RFSoC direct sampling (ZU48DR) datasheet p.3
Each value is typed with its unit and measurement condition and cites the datasheet page it was taken from. Nothing is guessed: a field that is absent here has not been published by the manufacturer. machine-extracted ✓ checked by NewSpace Market ✓ manufacturer confirmed by the manufacturer.
As published by the supplier19 lines, in the manufacturer's own wording
- Mpsoc
- Xilinx Zynq UltraScale+ ZU48DR
- Application cpu
- Quad-core ARM Cortex-A53 @ up to 1.2 GHz
- Real-time cpu
- Dual-core ARM Cortex-R5 @ 500 MHz
- Ps ram
- 4 GB LPDDR4 DRAM (EDAC)
- Pl ram
- 4 GB DDR4 DRAM
- Storage
- 2x 128 GB eMMC
- ADC channels
- 8
- ADC sample rate (max)
- 5.0 GSPS
- ADC resolution
- 14 bit
- DAC channels
- 8
- DAC sample rate (max)
- 9.85 GSPS
- DAC resolution
- 14 bit
- RF input frequency (max)
- 6 GHz
- Multi-device synchronization
- Supported (phased-array/digital beamforming)
- Dimensions
- 100 x 100 x 20 mm
- Mass
- 200 g
- Power (Typical)
- 25 to 35 W
- Supply voltage
- 5 to 15 V
- Operating temperature
- -40 to +60 deg C
About
The Xiphos Q8RFG3 is the third-generation RFSoC processor in the Q8RF family, built on the Xilinx Zynq UltraScale+ ZU48DR. It advances the Gen 1 platform with enhanced digitization performance — 14-bit ADC resolution at up to 5.0 GSPS and 14-bit DAC resolution at up to 9.85 GSPS — as well as an extended RF input frequency range to 6 GHz and expanded decimation and interpolation options.
Multi-device synchronization support enables phased-array and digital beamforming architectures requiring coherent operation across multiple Q8RFG3 boards. The architecture enables direct RF sampling and real-time DSP without external data converters or analog front-ends. Storage is upgraded to 2×128 GB eMMC for substantially higher onboard data capacity.
Physical dimensions and mass are identical to the Q8RF (100x100x20 mm, 200g), enabling drop-in mechanical upgrades for applications where the Gen 1 Q8RF’s 4 GHz frequency ceiling or 12-bit ADC dynamic range is insufficient.
Documentation
Need the full ICD, test reports or a specific revision? Ask the supplier directly.